Growing demands for extended battery life and high processing speeds in the handheld device and mobile phone industries have created a corresponding need for low power and high performance memory systems. In order to conserve power, on-chip memory is restricted to low supply voltage levels.
However, conventional memory cells such as 6 Transistor Static Random Access Memory (6T-SRAM) are not capable of operating at very low voltages. A common solution involves the use of multiple voltage domains, such that memory cells may be operated at a relatively high voltage level while other on-chip logic may be operated at lower voltages. In order to achieve multiple voltage domains, level shifters are commonly used to convert low voltage to high voltage and vice versa as needed. However, level shifters introduce latency, which may be undesirable in timing critical paths.
In the case of memory systems comprising large arrays of memory cells, locally generated self-timed pulse clocks are often utilized to overcome the effects of device variations (e.g. due to process variations). These pulse clocks may be subjected to conflicting needs for different memory access operations. For example, during a memory read operation it may be desirable for the rising edge of the pulse clock to arrive as fast as possible at memory cells of the memory array being accessed, in order to enable quick read access. Moreover, during the memory read operation it may be desirable for the pulse width of the pulse clock to be narrow, in order to reduce power consumption by disallowing full voltage swings on bit lines.
On the other hand, memory write operations are usually not timing critical, and thus can tolerate higher arrival delays in the rising edge of the pulse clock. In fact, memory write operations may benefit from delays in the pulse clock so as to allow sufficient set-up time for the data written. In further contrast to read operations, during write operations it may be desirable for the pulse width of the pulse clock to be wider to allow for sufficient write time in order to guarantee successful completion of the write operations, especially at lower supply voltage levels. Conventional pulse clock implementations are not well suited to meet these conflicting needs for read and write operations on memory cells.
Accordingly, there is a need in the art for solutions which avoid the aforementioned problems associated with level shifters and pulse clocks.